Research on Failure Mechanism of IC Smart Card

As a new high-tech storage product in the information age, IC smart card has the advantages of large capacity, strong confidentiality and portability, and is widely used in various fields of social life. The so-called IC card is formed by embedding an IC chip containing a non-volatile memory unit NVM or an integrated microcontroller MCU on a plastic substrate, mainly including a plastic substrate (with or without a magnetic strip), a contact surface. , IC chip 3 parts. The conventional IC card manufacturing process is: thinning and dicing a silicon wafer after testing and information writing, separating into small chips, and then forming an IC card module through processes such as loading, wire bonding, and encapsulation. Finally, the IC card plastic substrate is embedded.

With the improvement of the manufacturing process of IC products and the emergence of high-performance LSIs, IC smart cards are constantly developing in a diversified and intelligent manner to meet people's pursuit of convenience and speed. However, many invalidation problems such as password verification errors, data loss, data writing errors, garbled characters, all "0" all "F", etc. during use have seriously affected the wide application of IC cards. Therefore, it is necessary to analyze the failed IC card in combination with the manufacturing process and environment of the IC card, and deeply study its failure mode and failure mechanism, and explore the root cause of the failure, so as to take corresponding measures to improve the quality and performance of the IC card. 1.

From the analysis example of IC card failure samples, it is found that chip fragmentation, internal lead wire dropout (desoldering, virtual soldering, etc.), chip circuit breakdown and other phenomena are the main causes of IC card failure. This paper focuses on chip fragmentation of IC card. , Bond failure mode and mechanism for research and discussion, and briefly introduce other failure modes.

1 chip failure caused by chipping

Since the IC card uses a thin/ultra-thin chip, chip fragmentation is the main cause of its failure, accounting for more than half of the total number of failures. The main performance is that the IC card data is written incorrectly, garbled, and all "0" all "F".

Conduct electrical tests on 1739 failed IC cards provided by different companies, select 100 samples with failure modes of all "0" and "F" for positive and back corrosion opening of IC cards, and observe the crack shape by optical microscope (OM) observation. Most of them are "T" and "T", and some are single cracks running through the chip, and are slightly bent at the point of action of the thimble, as shown in Figure 1. The crack in the chip is more than 50%, located near the center of the chip and perpendicular to the edge; the cracks of the remaining chips are close to the edge of the chip or concentrated on the chip.

Figure 1 OM photo of the chip on the back of the chip

Chip chipping is ultimately caused by stress. When the external stress exceeds the chip chipping strength, the chip will undergo brittle fracture. Thinning, core, pressure welding and plastic sealing in the manufacturing process are the main processes that cause chip chipping. These processes are likely to cause micro cracks or damage on the surface of the chip, and stress concentration occurs when stress is applied, especially the vertical surface crack. Stress, mostly concentrated on the tip of the crack. When the stress exceeds the stress intensity factor of the chip, the microcracks lose stability and expand, which greatly reduces the strength of the chip.

In the following, according to the physical mechanism of chip fragmentation, combined with the IC card fabrication process (including the subsequent process of silicon wafer, module strip fabrication, IC card molding process), the root cause of chip fragmentation of IC card is analyzed in depth.

Figure 2 OM photo of the backside grinding damage of the chip

1.1 Silicon thinning

The standard silicon wafer back-thinning process includes three processes: patch, grinding (rough grinding, fine grinding) and corrosion. Commonly used mechanical grinding methods inevitably cause damage to the surface and subsurface of the silicon wafer (Fig. 2). The surface damage is divided into three layers: an amorphous layer with microcrack distribution; a deeper lattice dislocation layer; Deformed layer. After coarse grinding and fine grinding, a thin layer with a depth of 15-20 μm and micro-damage and micro-cracks remains on the back side of the silicon wafer, which greatly affects the strength of the silicon wafer. Therefore, it is necessary to remove the lattice damage layer remaining on the back side of the silicon wafer by etching to prevent the silicon wafer from being broken due to residual stress. It was found that the silicon wafer with the original thickness of 725μm can obtain the maximum strength value 3 after the etching depth is about 25μm. At the same time, the analysis shows that the chip breaks during bonding and testing, often due to the grinding sheet. The damage caused by the time is not completely removed in the subsequent corrosion or chemical mechanical polishing.

According to the Giffith microcrack propagation theory 4, the expansion criterion of the one-dimensional crack with length a is σ2≥2Eγsπa. If the residual crack on the back side of the chip is c, the Young's modulus E=106. 9GPa, surface energy Γs=3. 1J/m2 and other parameters are substituted, and the critical strength of chip fragmentation under plane stress state under normal load condition is σ=0.46/c(GPa), and Fig. 3(a) shows σ and chip back. Correspondence of residual crack length.

For a two-dimensional semi-elliptical crack with a fracture surface perpendicular to the surface of the chip, deep a and length 2b, Ccr=[(Φ2KIC2)/(1.2πσIC2)][2], where Ccr=(acrbcr)1 is satisfied. /2, acr is the critical crack depth, bcr is the critical crack half length; crack geometry factor Φ = (1. 2π) 1/2 / Y. Let the crack length be 2b, the depth constant is 1μm, substitute the fracture toughness KIC=0.82MPa, Y=1.42, the critical strength of the fragmentation under the plane stress state under normal load condition σ=0.58/4b(GPa) The corresponding relationship between σ and the residual crack length and depth on the back side of the chip is shown in Fig. 3(b). It can be seen that the critical strength of chip fragmentation decreases sharply with the increase of microcrack length. When the crack is larger than 1μm, the downward trend gradually becomes gentle and tends to be stable.

The grinding process not only causes microcracks on the back side of the wafer, but the residual stress on the surface also causes the wafer to warp. The backside thinning of the silicon wafer has a direct impact on chip fragmentation, so new technologies need to be developed to achieve backside thinning process integration to increase the efficiency of silicon thinning and reduce chip fragmentation.

Figure 3 Correspondence diagram of critical strength and length of fragmentation

1.2 dicing process

The thinned silicon wafer is sent to the dicing machine for dicing. The cross section of the dicing groove is often rough, and there are usually a small number of micro cracks and pits; in some places, there are even cases where the dicing sheet is not drawn to the bottom. It is necessary to rely on the top force of the thimble to make the chip "forced" to separate, and the fracture is irregular, as shown in Fig. 4 is an overlay of a plurality of samples. Experiments have shown that the damage caused by the dicing of the chip edge will also seriously affect the chip's chipping strength. For example, a chip with micro-cracks or grooves in the fracture, cracking due to the mismatch of thermal expansion coefficient (CTE) during the subsequent impact of the wire bonding process or the heat treatment after encapsulation causes the microcrack to expand and break. .

Figure 4 IC card chip dicing slot break (multi-image overlay)

In order to reduce the damage of the dicing process to the chip, new dicing techniques have been introduced: dicingbeforegrinding (DBG) and dicingbythinning (DBT)5, ie in silicon wafers. Before the back surface is thinned, the slit is cut on the front side by grinding or etching to achieve automatic separation of the chip after thinning. These two methods can well avoid/reduce wafer warpage caused by thinning and chip edge damage caused by dicing. In addition, the laser dicing technology using non-mechanical contact processing can also avoid micro-cracks, fragments and the like caused by mechanical dicing, and greatly improve the yield.

1.3 Module Process

During the loading process of the module process including loading, encapsulation, etc., the ejector pin of the loading machine lifts the chip from the patch film, and the chip is sucked by the vacuum suction head to bond it to the lead frame of the chip card. If the process parameters of the film loading machine are not properly adjusted, it will cause damage on the back side of the chip, which will seriously affect the chip strength: if the top pin is uneven or too large, the thimble will pierce the blue film and directly act on the chip, leaving a circle on the back of the chip. The type of damage pit; or the thimble has a certain amount of equal slip on the back of the chip, leaving a large area of ​​scratches, which accounts for a considerable proportion of the chip.

Fig. 5 Relationship between the maximum value of the tension component of the chip and the contact radius during the action of the thimble

Fig pin action can be equivalent to the Vicker indenter 4 ballast process, which will cause local damage to the chip surface. Now, the top touch process for the back of the chip (not considering the slip of the thimble) is simplified to the ideal case of vertical loading of the spherically symmetric plane. The change of the radius a of the contact circle with the vertical load P is a=34PR(1- V2)/E+(1-v'2)/E'1/3=αP1/3, where R is the thimble end radius, E, v and E', v' are the chip and thimble end of Young's Modulus and Poisson's ratio. At the edge of the contact circle, the tensile stress component of the chip reaches a maximum value σm=12(1-2v)P0, where P0=P/πα2 is the vertical stress applied to the end, and σm acts in the radial direction and with the material. Surface equal stress. Since the tip of the thimble has a small radius, the silicon material is v=0.28, and the corresponding relationship between the maximum value of the chip tension component and the contact radius is obtained by the 1N top force. It can be seen that in the initial case, the contact radius is small, and the initial value of the chip tension component can reach the order of GPa. Compared with the previous calculation results, the thimble process is a major cause of chip fragmentation.

At a specific contact radius, the tensile stress outside the contact surface of the chip surface satisfies σr=σm(a/r)2 between the radial distance from the contact center, and decreases as the radial distance r from the contact center increases. Therefore, in a certain range from the point of action of the thimble, there is still a tensile stress surface layer on the surface of the chip, which provides a very favorable condition for crack generation and expansion.

In addition, with the effect of indentation, the chip often breaks, that is, some materials around the indentation are crumb-like. When the thimble acts, the deformation zone under the surface of the indentation will have a transverse crack. After the indentation disappears, the transverse crack will proliferate up to the surface of the sample, resulting in fragmentation. Under normal circumstances, the greater the pressure, the more serious the fragmentation phenomenon.

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